1. Field of the Invention
The present invention relates to a configurable interface enabling straightforward re-use of a core with different interfaces.
2. Art Background
The latest advances in semiconductor technology and design methodology have enabled the emerging market for System-On-a-Chip (SoC) designs. Full systems, consisting of more than several million logic gates, can now be implemented in a single chip. One of the main design challenges in these SoC designs is the logical and physical interconnect that allows communication between the subsystem cores that compose the design. These cores typically fall into different categories: computing cores such as a CPU (central processing unit), DSP (digital signal processor) or floating point co-processor; peripheral interface cores such as PCI (personal computer interface) or USB (universal serial bus); memory blocks such as SRAM (static random access memory) and on-chip DRAM (dynamic random access memory); and application specific blocks such as video cores (MPEG-motion pictures experts group) or communication cores.
Since many of the SoC designs are targeted towards communications and consumer applications, time-to-market is a critical factor in the decision process on the level of integration to be used in a particular product. Once a core has been proven in one design, it becomes very attractive to re-use the core in later designs. While choosing a proven design may eliminate the time that would otherwise be required to design a new core, design re-use offers the promise of many other benefits. First, a model may be written for the proven core that can provide accurate results when analyzing the requirements and performance of a new system design; the model for a new, unproven core is likely to be neither as accurate as the proven core, nor built in time to influence the design. Second, proven cores can serve as building blocks that simplify the overall design process by allowing the system designer to focus at a higher level of abstraction, while providing improved predictability in the resulting system implementation. Third, re-use of hardware cores protects the investment in software to control those cores, and allows the system software implementation to proceed as soon as the hardware building blocks have been chosen. Finally, core re-use protects the investment in verification and testing. Since the desired systems are highly integrated, the required cores end up deeply embedded within an integrated circuit. In deeply-embedded designs, verifying the design functionality becomes very challenging and testing an individual system to prove that it is correctly built can lead to expensive delays or costly system rework. Thus, maintaining the integrity of core verification and testing is likely the single biggest gain from design re-use.
However, historically, re-using cores has not been efficient. One of the challenges in the re-use of these cores is that, dependent on the system requirements of the SoC that the core is used in, different performance levels and features are required from the core. Moreover, many applications of SoC are targeted towards consumer applications where providing the most cost-effective solution is very important.
The interface of the core has been a source of inefficiency in core re-use. FIG. 1a shows a representation of a core with a particular interface. Inefficiencies arise when this core must be re-used in a different system that requires a different interface of the core, or demands different requirements of the core.
One option is to re-design the interface of the core. This solution may offer area and performance benefits, but is expensive in term of time, effort and design risk. The effort involved is not only in terms of design time but there is also significant additional work in verification and validation. This solution is represented in FIG. 1b, which shows the core with the optimized interface.
Rather than changing the core, some designers opt to leave the core as is, and adapt the system level interconnect to the existing core interface. While it preserves the integrity of the original core, it leads to many other inefficiencies. With respect to performance, the logic that integrates the core into the system can add latency into the system, which can adversely affect the system performance. With respect to cost, the additional logic can add a significant number of gates to the design and hence increase the chip area and hence the cost. This solution is represented in FIG. 1c. 